1. Field
One or more embodiments herein relate to a delay-locked loop circuit.
2. Description of the Related Art
One type of memory that has been developed is known as a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). Such a memory performs an ODT (On-Die Termination) operation to read data in synchronization with an external clock or to vary a termination resistance value. A delay-locked loop (DLL) circuit has been used to control the clock synchronization operation. A DLL having a coarse-fine architecture has been extensively used to improve a DLL lock time.
A DDR4 SDRAM has an operation range of 1.6 GT/s to 3.2 GT/s and has an operation voltage of 1.2 V or less. Under the above condition, quality degradation in an input clock may have a pronounced effect on overall operation of the DLL. An example of such quality degradation is coarse-lock failure due to jitter of the input clock.